Frequency shift keying (“FSK”) demodulation is a conventional technique used in communications technologies to modulate the frequency of a signal in order to transmit or send data. By modulating the frequency of a communication signal, a communications signal can be used to transmit data, often in the form of binary data using various types of communications networks, analog, POTS, etc. In general, there are particular requirements for communications processors using FSK demodulation.
The performance of a FSK demodulator integrated on an IC requires stability, particularly with regard to the bit error rate (“BER”), which must be stable during changes in time, process, and temperature. A FSK demodulator must also eliminate any DC voltage offset in a demodulator unit created by precision errors and errors in the frequency synthesizer bit rate. These errors can occur consistently at the beginning or in the middle of data reception. Elimination of errors resulting from non-ideal reception paths for the FSK receiver is another purpose for using FSK demodulators. In addition, a wireless FSK demodulator also maintains power requirements which are distinct from other conventional FSK demodulators. Specifically, lower power consumption rates are desired and power requirements should be suitable for the data rate of the FSK modulation signal that is to be demodulated, index modulation, and intermediate frequency (IF) of the demodulator.
FIG. 1 illustrates a conventional demodulating circuit, including a band-pass filter, a zero crossing detector, an average characteristic detector, and a signal decider, which counts the number of zero crossing points. Counting the number of zero crossing points is based on whether the number of higher frequency FSK demodulation signal zero crossings is greater than the number of lower frequency zero crossings. For an FSK demodulation method, the number of zero crossing points is also based on the change in the zero crossing count.
FIG. 2 is a diagram illustrating a conventional demodulating method wherein a zero crossing can be counted using a sampling clock that is much faster than the IF frequency. A problem with this method is the requirement for a very high sampling clock if an IF frequency is high and the modulation index is small. For example, if an IF frequency is 3 MHz, the data rate is 1 Mbps, and the modulation index is 0.3, the two FSK frequencies to be demodulated by the zero crossing detector are 2.85 MHz and 3.15 MHz, which require a sampling frequency several times higher than 30 MHz.
FIG. 3 is a block diagram of a conventional FSK demodulation circuit. FIG. 4 is a block diagram of a conventional DC offset remover, which uses an adaptive method for a comparative value that is used as a reference in the signal decider of FIG. 1. The comparative value is the average of the maximum and the minimum output of the said average characteristic detector of FIG. 1.
FIG. 5 illustrates an IC for implementing a conventional FSK demodulation method. As illustrated, a bit slice method is used whereby a signal from an amplitude limiter is multiplied by a signal that passes through a 90 degrees phase shifter or a T/4 delay line. The signal then passes through a low pass filter (LPF), and is compared with a threshold voltage. However, there are problems associated with designing a reliable phase shifter using the IC of FIG. 5. If the modulation index is small, one disadvantage in IC design using the IC of FIG. 5 is the requirement for a phase shifter of high Q value because the distance between the two frequencies of the FSK modulation signal intended for demodulation is close. If a delay line is used that has a delay time of T/4, the phase shift is also problematic with regard to the output signal of the multiplier. Specifically, if a delay time of T/4 is used, the phase shifter may require an LPF of high attenuation ratio because of the relatively high harmonics in the output signal of the multiplier.